DAC38J84EVM Data Conversion IC Development Tools DAC38J84 EVAL MO Data Conversion IC Development Tools DAC38J84 EVAL MOD

Functional Description
The DAC3XJ8XEVM is intended for evaluation of the DAC3XJ8X family of high-speed, JESD204B interface DACs. The digital input signal to the DAC is provided from the FMC connector (J16) on up to eight 12.5-Gbps SerDes lanes using the JESD204B interface standard. The FMC connector is also used for the SYNC signal required to establish the JESD204B link and both device clock and SYSREF signal for the FPGA.
The analog output of the DAC3XJ8X can be monitored on the installed SMA connectors labeled IOUTA through IOUTD for channels A through D, respectively. The analog outputs are transformer coupled and do not pass low frequency signals below approximately 10 MHz. The transformer converts the differential DAC output to a single-ended output for use with common laboratory equipment through wired SMA cable connections.
The clocks for the DAC and FPGA are distributed using the LMK04828 ultra low-noise clock jitter cleaner for JESD204B applications. The LMK04828 can be setup in a variety of configurations including clock distribution mode and dual-loop jitter cleaning mode. In clock distribution mode, the desired DAC output rate is provided to the CLKIN connector and the LMK04828 divides and distributes the device clocks and SYSREF signals. In dual-loop mode, the CLKIN connector can be used to provide a reference to the LMK04828, but the clocks are generated on board using the LMK04828 PLL and onboard 122.88 MHz VCXO.