BCM82381BKFSBG RF Integrated Circuits Ethernet ICs 28nm 25/28G
Duplex Retimer - 19x19 pkg
Overview
The Broadcom® BCM82381 is a low-power, low- latency PHY integrating
retimer and equalizer func- tions that support 100-Gigabit Ethernet
(GbE), 40GbE, and 10GbE applications. In 100G mode, the BCM82381
supports two full-duplex 100G ports (CAUI4-to-CAUI4) for SR4, LR4,
and copper CR4 CFP2/CFP4/QSFP2 line-card applications. In 40G mode,
the BCM82381 supports two full-duplex 40GbE ports (XLPPI-to-XLAUI)
for SR4, LR4, and copper CR4 QSFP+ line-card applications. In 10G
mode, the BCM82381 supports eight full-duplex 10GbE ports
(SFI-to-XFI) for SR, LR, and copper CR SFP+ line-card applications.
On-chip clock synthesis is performed by a dual low- cost 156.25 MHz
reference clock (for all IEEE Stan- dard 10G/40G/100G rates) via
high-frequency, low- jitter phase-locked loops (PLLs). Individual
clock recovery is performed on the device by synchroniz- ing
directly to the respective incoming data streams.
The BCM82381 was designed in 28 nm CMOS tech- nology to provide a
low-power (<2.5W per 100G full-duplex port, including 100G FEC),
low-latency (<5 ns round trip) solution with integrated AC cou-
pling capacitors for direct interfacing to Broad- com’s switch
products.
The BCM82381 is available in a 19 mm x 19 mm, 324-pin BGA,
RoHS-compliant package.
Features
Dual 100GbE ports with CAUI4-to-CAUI4 port support SR4/LR4/CR4
CFP2/CFP4/QSFP2 retimer/equalization applications.
Dual 40GbE channels with two XLPPI-to-XLAUI ports support
SR4/LR4/CR4 QSFP+ retimer/ equalization applications.
10G mode with eight independent 10GbE/ 1GbE SFI-to-XFI channels
support SR/LR/CR SFP+ retimer/equalization applications. Sup- ports
an intermix of 1GbE and 10GbE opera- tions on a per-lane basis.
Low-latency design (<5 ns round trip).
• Low-power retimer/equalizer PHY (<2.5W per 100GbE
bidirectional port, including 100G FEC; equivalent to <300 mW
per 25G unidirectional channel for 25G retiming mode).
• Seamless high-speed I/O routing to modules. • Integrated
AC-coupling capacitors on all high-
speed receivers.
• High-performance receive equalization ~30 dB
at system side and ~35 dB at line side for chan-
nel loss.
• Programmable transmit preemphasis for flexi-
ble PHY placement.
• IEEE 802.3bj 100GbE CR4 Clause 92 transmit
training; IEEE 802.3ba 40GbE CR4 Clause 85
transmit training.
• Supports IEEE 802.3bj Clause 91 Forward Error
Correction (FEC) and bypassable.
• Supports Fibre Channel rates: 32G/16G/8G/4G
FC.
• Supports individual 25G lane retiming mode. • Line-side and
system-side loopbacks.
• Single low-cost 156.25 MHz reference clock. • Standard two-wire
serial interface (BSC) sup-
port for external modules.
• Low-speed module I/O control signals for
CFP2, CFP4, and QSFP2.
• MDIO interface compliant with IEEE 802.3ae
Clause 45 with extended indirect address reg-
ister access.
• Advanced diagnostics, including eye-mapping
and BER with PRBS generators/checkers. • Dual-supply
operation—1.0V/3.3V.
Applications
High-density line cards support 100GbE CAUI4- to-CAUI4, 40GbE
XLPPI-to-XLAUI, and 10GbE SFI-to-XFI
100GbE CPF2/CFP4/QSFP2 optical and copper interfaces support SR4,
LR4, and copper CR4
40GbE QSFP+ optical and copper interfaces support SR4, LR4, and
copper CR4
10GbE SFP+ optical and interfaces support SR, LR, and CR
application
