EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs

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EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs

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EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs

EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs

Cyclone III Device Family Architecture

Cyclone III device family includes a customer-defined feature set that is optimized for portable applications and offers a wide range of density, memory, embedded multiplier, and I/O options. Cyclone III device family supports numerous external memory interfaces and I/O protocols that are common in high-volume applications. The Quartus II software features and parameterizable IP cores make it easier for you to use the Cyclone III device family interfaces and protocols.

The following sections provide an overview of the Cyclone III device family features.

Logic Elements and Logic Array Blocks

The logic array block (LAB) consists of 16 logic elements and a LAB-wide control block. An LE is the smallest unit of logic in the Cyclone III device family architecture. Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables.

Memory Blocks

Each M9K memory block of the Cyclone III device family provides nine Kbits of on-chip memory capable of operating at up to 315 MHz for Cyclone III devices and up to 274 MHz for Cyclone III LS devices. The embedded memory structure consists of M9K memory blocks columns that you can configure as RAM, first-in first-out (FIFO) buffers, or ROM. The Cyclone III device family memory blocks are optimized for applications such as high throughout packet processing, embedded processor program, and embedded data storage.

The Quartus II software allows you to take advantage of the M9K memory blocks by instantiating memory using a dedicated megafunction wizard or by inferring memory directly from the VHDL or Verilog source code.

M9K memory blocks support single-port, simple dual-port, and true dual-port operation modes. Single-port mode and simple dual-port mode are supported for all port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36. True dual-port is supported in port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, and ×18.

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EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs

EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs

EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs

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EP3C55F484C8N EP3C55U484I7N Programmable Logic ICS Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs