LPC1768FBD100 MCU Chips IC MCU 32BIT 512KB FLASH 100LQFP
Product Descriptions:
The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based
microcontrollers for
embedded applications featuring a high level of integration and low
power consumption.
The Arm Cortex-M3 is a next generation core that offers system
enhancements such as
enhanced debug features and a higher level of support block
integration.
The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100
MHz. The
LPC1769 operates at CPU frequencies of up to 120 MHz. The Arm
Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture
with separate local
instruction and data buses as well as a third bus for peripherals.
The Arm Cortex-M3 CPU
also includes an internal prefetch unit that supports speculative
branching.
The peripheral complement of the LPC1769/68/67/66/65/64/63 includes
up to 512 kB of
flash memory, up to 64 kB of data memory, Ethernet MAC, USB
Device/Host/OTG
interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN
channels, 2 SSP
controllers, SPI interface, 3 I 2 C-bus interfaces, 2-input plus
2-output I 2 S-bus interface,
8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature
Encoder interface,
four general purpose timers, 6-output general purpose PWM,
ultra-low power Real-Time
Clock (RTC) with separate battery supply, and up to 70 general
purpose I/O pins.
The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin
LPC236x Arm7-based
microcontroller series.
Features:
Arm Cortex-M3 processor, running at frequencies of up to 100 MHz
(LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory
Protection Unit
(MPU) supporting eight regions is included.
Arm Cortex-M3 built-in Nested Vectored Interrupt Controller
(NVIC).
Up to 512 kB on-chip flash programming memory. Enhanced flash
memory accelerator
enables high-speed 120 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP)
via on-chip
bootloader software.
On-chip SRAM includes:
32/16 kB of SRAM on the CPU with local code/data bus for
high-performance CPU
access.
Two/one 16 kB SRAM blocks with separate access paths for higher
throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as
well as
for general purpose CPU instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB
multilayer
matrix that can be used with SSP, I 2 S-bus, UART,
Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, and
for
memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for
each AHB master.
AHB masters include the CPU, General Purpose DMA controller,
Ethernet MAC, and
the USB interface. This interconnect provides communication with no
arbitration
delays.
Split APB bus allows high throughput with few stalls between the
CPU and DMA.
Parametrics:
Applications
eMetering Alarm systems
Lighting White goods
Industrial networking Motor control
LPC1769 LPC1768
LPC1767 LPC1766
LPC1765 LPC1764 LPC1763
